At a glance
| Booth | M1040 |
| Country | KR |
| Website | www.semes.com |
Company profile
SEMES Co., Ltd. identifies itself as a Korean manufacturer of semiconductor and flat panel display equipment and describes its position as the largest and most advanced leader among such equipment manufacturers in Korea. Since 1993, SEMES Co., Ltd. has continuously invested in research and development for high-end technology with the stated objective of producing quality equipment. The company also connects that research and development investment with the delivery of high levels of products and services intended to meet customer needs in semiconductor and display equipment environments.
Exhibits
In wafer cleaning, SEMES Co., Ltd. describes the removal of impurities from wafer surfaces through chemicals, gases, and physical methods as a crucial semiconductor process because particles, metals, organic substances, and natural oxides can create pattern defects or deteriorate electrical properties. The listed contamination sources include material entering from the external environment and impurities generated during semiconductor manufacturing, and even trace contamination can reduce semiconductor yield and reliability as well as damage pattern and electrical characteristics. Cleaning is repeatedly performed before and after wafer processes and is described as occurring about twice as often as other processes, acting as a bridge between successive wafer-processing steps. As micro-processing becomes more advanced and process materials change, single-wafer spray processing is taking a larger role, while different impurity types on the wafer surface require multiple cleaning methods to be applied. The photo process, or photolithography, uses a mask image and light containing the circuit pattern to form circuit patterns on the wafer surface, and SEMES Co., Ltd. describes this fine-pattern work as requiring sophisticated, high-level technology. Photolithography is divided into coating, exposure, and development: photoresist is applied uniformly to the wafer, light passes through a patterned mask to transfer the circuit, and developer selectively removes exposed and non-exposed areas. Etching forms semiconductor circuit patterns by using a liquid or gaseous etchant to remove wafer areas that are not protected by the photoresist pattern formed in the photo process. The etch flow includes dry etching with reactive gases and ions and wet etching with chemical solution, and dry etching is being applied more broadly as semiconductor technology moves toward high integration at the nano scale. Electrical Die Sorting is performed between the FAB process and the packaging process to determine whether individual chips have reached the desired quality level before final product packaging. The objectives of Electrical Die Sorting include selecting wafer-state chips by quality, recovering repairable defective chips, correcting problems found in FAB or design, and improving packaging and test efficiency through early screening of faulty chips. The EDS process uses a probe card whose many fine pins contact the wafer and send electrical signals that are used to identify defective chips. In packaging, wafer-state chips are separated into individual chips, connected to substrates, and molded to protect the chips while enabling interconnection, power supply, and heat dissipation. The package process also protects integrated circuits from high temperature, impurities, and physical shock and is divided into steps including Wafer Sawing, Die Attach, Bonding, Molding, and Sawing. Packaging gives integrated circuits an appropriate form for mounting at required positions on substrates or electronic devices while also combining mechanical protection with interconnection, power delivery, and thermal-management functions.
Capabilities and products
- wafer cleaning process equipment
- photolithography process equipment
- dry and wet etch process equipment
- Electrical Die Sorting equipment