At a glance
| Booth | I2723 |
| Country | CN |
| Website | www.fsm-sh.com |
Company profile
Fine Silicon Manufacturing (Shanghai) Ltd. was established in 2008 and is headquartered in the Shanghai Waigaoqiao Free Trade Zone, and it is described as one of the earliest enterprises in China engaged in silicon-wafer processing and sales. KOD Corporation was established in Tokyo in 2015, and the FSM Group operates production bases in Shanghai and Tokyo. On the sales side, FSM and KOD cooperate with domestic and overseas upstream wafer makers, wafer reclaim houses, and downstream semiconductor foundries, with customers across domestic and foreign markets. FSM's business developed beyond an initial single Dummy wafer focus as its wafer-processing and sales activities expanded into additional services and material categories. The company has also expanded its semiconductor-material activities into the field of third-generation semiconductors.
Exhibits
FSM supplies dummy wafers from 2 inches to 12 inches, with its own factory used to support stable quality and controllable delivery time, and parameter testing can be provided through its testing equipment. The dummy-wafer specification page lists 150 mm, 200 mm, and 300 mm diameters, P/N types, SEMI/JEIDA notch or OF configurations, polished surfaces with etched backs, and CoinRoll packaging. For these dummy wafers, listed thickness values include 675±25/625±25 μm at 150 mm, 725±25 μm at 200 mm, and 775±25 μm at 300 mm. FSM provides wafer-reclaim services from 6 inches through 12 inches and supplies Test, Control, and Dummy wafers in multiple sizes. Customized coated wafers are available in different sizes and film thicknesses, with listed film options including Thermal oxide, PETEOS, LP-Nitride, PE SiN, W, ECP-Cu, AL, and PR. FSM also offers silicon thermal-oxide wafers produced through either Wet Thermal Oxide or Dry Thermal Oxide processing to grow a Thermal Oxide, or Silicon Dioxide (SiO2), layer on the wafer surface. Test grade wafers are positioned below prime grade wafers in quality, with cleanliness and flatness requirements that are less rigorous than prime grade material, and they are used to monitor the performance and status of semiconductor process steps or to provide a more economical option for isolated testing. The test-grade page covers 150MM, 200MM, and 300MM wafers and lists, among other parameters, resistivity of 1-100 Ω・cm, thickness of 675um±25um or 625um±25um for the 150MM variants, 725±25 for 200MM, and 775±25 for 300MM. It also specifies TTV values of ≤30um for the 150MM variants and ≦25 for the 200MM and 300MM variants, with BOW and WARP values of ≤40um in the listed test-grade specifications. FSM's SOI (Silicon-On-Insulator) wafers combine a top device silicon layer, a buried oxide (BOX) layer, and a handle silicon layer and are available from 2 inches to 8 inches. The SOI line specifies thickness tolerance of ±5%, TTV below 5μm, bow below 20μm, P-type, N-type, or intrinsic doping choices, and resistivity from 0.001 to over 20,000 Ω·cm. SOI applications listed by FSM include advanced CMOS logic and low-power ICs, RF front-end and high-frequency devices, MEMS sensors and actuators, and power semiconductor devices requiring dielectric isolation, with support for R&D prototyping and mass production. The SOI device and handle layers can use CZ or FZ crystal growth, with (100), (110), and (111) orientations; the listed BOX thickness spans 0.1μm to 3μm, while handle-layer thickness spans 200μm to 750μm. FSM's InP (Indium Phosphide) wafers are grown by the Vertical Gradient Freeze (VGF) method in 2-inch, 3-inch, and 4-inch sizes with <100> orientation and undoped, N-type S/Sn, or P-type Zn options. The InP wafers are epi-ready with polished or etched surfaces, and the listed performance controls include TTV of ≤10 μm for 2 inch and ≤15 μm for 3 inch and 4 inch, with bow and warp controlled to ≤15 μm. InP application examples include laser diodes and photodetectors for optical communication, high-frequency and high-electron-mobility transistors, photonic integrated circuits, and substrates for multi-junction solar cells. FSM's InSb (Indium Antimonide) wafers use the VGF method in 2-inch and 3-inch diameters with <100> orientation, with undoped, N-type S/Sn, and P-type Zn variants and polished or etched epi-ready surfaces. The InSb specifications list TTV, bow, and warp controls of up to 15 μm, with the 2-inch TTV listed at ≤10 μm, and the wafers are intended for infrared detection and sensing applications. InSb application examples include infrared detectors and focal-plane arrays, Hall-effect sensors and magnetoresistive devices, thermal-imaging systems, and high-speed, low-power electronic devices. The broader wafer portfolio also includes GaN wafers grown by Hydride Vapor Phase Epitaxy with semi-insulating Fe-doped and N-type Ge-doped or undoped variants, C-plane <0001> orientation, EPD as low as 1~9E5/cm², front-surface roughness Ra ≤0.2nm, TTV ≤15μm, and bow and warp ≤20μm for power and RF device applications. FSM also lists InAs wafers grown by VGF in 2-inch, 3-inch, and 4-inch diameters with <100> and <111> orientations, undoped and N-type S/Sn or P-type Zn variants, TTV ≤15μm, bow ≤10μm, warp ≤15μm, and polished or etched surfaces for infrared and high-speed electronic device applications. Together with SiC, LiTaO3 (LT), LiNbO3 (LN), glass wafers, wafer polishing, reclaim services, test and control wafers, and custom film coatings, these products connect FSM's silicon-wafer processing base to semiconductor process monitoring, substrate preparation, specialty materials, and device-development applications.
Capabilities and products
- 2–12-inch dummy wafers
- 6–12-inch wafer-reclaim service agency
- Test/Control/Dummy wafer supply
- custom Thermal oxide wafers
- PETEOS/LP-Nitride/PE SiN coated wafers
- W/ECP-Cu/AL/PR custom coated wafers
- wafer parameter-testing services
- test-grade silicon wafers
- 2–8-inch SOI wafers
- HVPE-grown GaN wafers
- VGF-grown InP wafers
- VGF-grown InSb wafers
- wafer polishing services
- SiC/LiTaO3/LiNbO3 wafers