At a glance
| Booth | Q6134 |
| Country | JP |
| Website | www.t-microtec.com |
Company profile
Tohoku-MicroTec Co., Ltd was established on April 2, 2010 with capital of 9,300,000 yen and has its headquarters in Sendai, Miyagi, Japan. The company is a foundry specializing in 3D-IC manufacturing and provides 3D-ICs by applying TSV, redistribution, UBM, and bumping technologies to customer IC chips and IC wafers up to 12 inches in size. It also provides prototyping for Si interposers, heterogeneous stacked devices, chiplets, and other devices using the same technologies. Its business includes 3D Stacking LSI prototype manufacturing service, development of bio-electronic devices for neuroscience, and consulting for 3D Stacking LSI process development, with Koyanagi Lab, the New Industry Creation Hatchery Center, and Tohoku University listed as partners. The company researches and manufactures stacked three-dimensional LSI integration technologies and uses element technologies including TSV formation through etching, plating, and insulating-film formation, bump formation from 20 μm down to below 2 μm, and bonding from chips through 12-inch wafers. Its fine-pitch Au micro-bump work targets versatile bonding of silicon LSI, compound-semiconductor, and microelectromechanical-system devices at temperatures below 200 °C for heterogeneous integration without causing crystal damage. It combines technologies including TSV, μ-bumps, and RDL to design 3D-IC layouts and integration processes without degrading base IC chips, and is developing high-precision, ultra-high-speed CtW stacking based on self-assembly together with what it describes as the world's smallest-pitch Au bump bonding technology. Public-support records list “brain probe” as selected under the FY2010 Strategic Core Technology Advancement Program for August 2010 to March 2013, “three-dimensional LSI” as selected under the FY2011 Strategic Core Technology Advancement Program (second call) for December 2011 to March 2014, “flexible interposer” as selected under the FY2012 Regional Innovation Creation Demonstration Research subsidy program for September 2012 to March 2014, and “practical-application development of sensor-fused three-dimensional LSI” under the FY2013 NEDO Innovation Commercialization Venture Support Program for June 2014 to February 2015. The same records list the FY2014 supplementary-budget Manufacturing, Commerce and Service Innovation Subsidy for July 2015 to March 2016, “micro-bump” as selected under the FY2015 Strategic Core Technology Advancement Program (second call) for October 2015 to March 2018, the FY2015 supplementary-budget Manufacturing, Commerce and Service New Development Support Subsidy for July 2016 to December 2016, “micro LED display” as selected under the FY2017 Strategic Core Technology Advancement Program for October 2017 to March 2020, the FY2016 supplementary-budget Manufacturing, Commerce and Service New Development Support Subsidy for May 2017 to December 2017, and the FY2017 supplementary-budget Manufacturing, Commerce and Service New Development Support Subsidy for May 2018 to December 2018. They also list “low-cost / high-throughput TSV formation technology” under the FY2018 JST A-STEP (Adaptable and Seamless Technology Transfer Program through Target-driven R&D) Seeds Development type for October 2018 to March 2021 and “development toward the practical application of AI-chip ideas” under the FY2018 NEDO Innovation Promotion Program for Accelerating AI Chip Development.
Exhibits
Fine-pitch Micro-TSV processing uses tungsten as a suitable conductor when TSVs are formed after the MOS device, and tungsten, copper, and other materials when TSVs are formed after the FEOL process; the process emphasizes low-temperature formation of sidewall insulators plus contact and barrier metals for high-aspect-ratio TSVs. Its fine-pitch μ-TSV uses an O3-TEOS CVD insulator layer, with a conformal silicon-dioxide layer formed by reaction at the silicon surface at a relatively low temperature of -350℃. A stacked-TEG example joins upper and lower chips with adhesive and 5 μm-pitch μ-bumps to integrate a 10^4 daisy-chain pattern; the bump size is 2 μm×2 μm, the adhesive completely fills a 0.5 μm chip gap, bump resistance is below 0.2 Ω, and temperature cycling at -65 ℃/150 ℃ showed no degradation through 500 cycles. Another prototype manufactured through the 3D-Stacking LSI prototype service uses μ-bumps measuring 3 μm×3 μm with 13 μm pitch. The prototype-friendly 3D-IC foundry service is provided to worldwide clients including company research divisions, universities, and research laboratories, and can perform any or all of TSV, RDL, bumping, thinning, and bonding as full-process or partial-process service, including single-wafer or single-die processing for initial research projects. Supported stacking methods are Wafer to Wafer (WtW), Chip to Wafer (CtW), and Chip to Chip (CtC), with 12-inch, 8-inch, 6-inch, and 2-inch wafers. TSV options include VIA-Last as the main method plus VIA-First and VIA-Middle, Cu and Poly-Si conductors, aspect ratio up to 1:10, and optical TSV; bump options include various solders, Cu pillar with cap, Au, and Au/In, while bonding includes melt and solid diffusion and RDL supports 1 to 2 layers without CMP or up to 4 layers with CMP. Unique foundry services include multi-chip bonding by self-assembly and ultra micro-bumps using Au cone or cylinder bumps with greater than 2.5 um size and greater than 5 um pitch. Si interposer fabrication is available from a one-wafer order for 8-inch or 12-inch wafers, with interposer size around 36 x 26 mm and stitching for larger sizes including an actual 50x50 mm result. For Si interposers, Cu TSV specifications are 50 to 200 um depth, 5 to 20 um diameter, and 10 to 40 um pitch; TSV-Last is the main method with TSV-First listed as TBD, RDL combines Cu damascene and Cu electroplating, and bump options include solder, Cu pillar with cap, Au, and Au-In. The partial-process service uses a 200/300 mm wafer 3D-IC, Si-Interposer, and MEMS line with lithography using an i-line stepper with IR alignment, Si/SiO2 deep etch, CVD for TSV liners, sputtering, electroplating, metal etch, temporary bonding, and temporary debonding. Available partial processes include wafer thinning, TSV making, Si/SiO2 deep trench processing, bump formulation, RDL with Cu damascene, and bonding.
Capabilities and products
- 3D-IC foundry service
- TSV/RDL/UBM/bumping processing
- Si interposer prototyping
- heterogeneous stacked device prototyping
- chiplet prototyping
- fine-pitch Au micro-bump bonding
- self-assembly CtW high-speed stacking
- Wafer-to-Wafer 3D stacking
- Chip-to-Chip 3D stacking
- TSV fabrication service
- RDL redistribution service
- wafer thinning service
- Si/SiO2 deep trench processing
- wafer bonding service