At a glance
| Booth | Q6134 |
| Country | JP |
| Website | www.t-microtec.com |
Company profile
Foundry specializing in 3D-IC manufacturing We provide 3D-ICs by applying TSV, redistribution, UBM, and bumping technologies to our customers' IC chips and IC wafers up to 12 inches in size. We also offer prototyping services for Si interposers, heterogeneous stacked devices, chiplets, and other devices using the same technologies. Core Technology Low cost 3D-Soc Manufacturing Technology Fine pitch Au micro-bump connection：We focus on a versatile bonding technology for silicon LSI, compound semiconductor, and microelectromechanical system devices at temperatures of less than 200 °C for heterogeneous integration w/o causing crystal damage. Our new gold (Au) micro-bump technology is one of the promising candidates for this purpose. We propose optimal solutions for 3D-IC by combining individual technologies such as TSV, μ-bumps, and RDL to design layouts and integration processes without degrading base IC chips. In addition, we are developing cutting-edge technologies such as high-precision, ultra-high-speed CtW stacking technology using self-assembly principle and the world's smallest pitch Au bump bonding technology.
Exhibits
Provides 3D-IC foundry services applying TSV, redistribution (RDL), UBM, and bumping technologies to customer IC chips and wafers up to 12 inches. Also offers prototyping for Si interposers, heterogeneous stacked devices, and chiplets, with fine-pitch Au micro-bump bonding and CtW stacking technologies.
Capabilities and products
- foundry specializing in 3D-IC manufacturing
- TSV through-silicon via technology
- redistribution, UBM and bumping technologies
- IC wafers up to 12 inches in size
- prototyping services for Si interposers
- heterogeneous stacked devices and chiplets
- low cost 3D-SoC manufacturing technology
- fine pitch Au micro-bump connection
- heterogeneous integration at temperatures below 200 °C
- bonding for compound semiconductor and MEMS devices
- combining TSV, micro-bumps and RDL for 3D-IC layout design
- ultra-high-speed CtW stacking using self-assembly