At a glance
| Booth | M0957 |
| Country | TW |
| Website | www.icometrue.com |
Company profile
iCometrue Company Ltd. was founded in 2012 with a mission to inspire, imagine, innovate, and invent fundamental, disruptive, and positive technology, while also exploring the development of semiconductor integrated-circuit chips under Moore's law and promoting Ethic Engineering to address possible misuse of increasingly powerful IC technology. Its major technology projects are Logic Drive, Field Programmable MultiChip Package (FPMCP), Glass Panel with embedded Through-Glass-Via (TGV) Connectors, and Ultra-Thin Vapor Chamber (UTVC), covering programmable logic packaging, advanced heterogeneous multi-chip integration, glass-based interconnection, and thin-film thermal solutions. The Logic Drive concept packages one or more FPGA chiplets fabricated by technology more advanced than 10 nm together with a Non-Volatile Memory (NVM) chip that stores FPGA configuration and re-configuration data in one multi-chip package. iCometrue Company Ltd. proposes standardizing the FPGA chiplet in the Logic Drive as a commodity product similar to DRAM or Flash memory so that advanced-process programmable logic can be made more cost effective, user friendly, and broadly accessible. One Logic Drive objective is to restore a Public Innovation Platform for semiconductor foundry users, allowing creative IC designers with limited funding to participate in designs using advanced process technologies such as 7 nm or 5 nm by configuring FPGA hardware and storing programming codes in non-volatile flash memory within the same package. The configured non-volatile Logic Drive is described as capable of being sold as an ASIC chip, while the broader concept aims to turn logic into a standard commodity model analogous to the DRAM and Flash memory industries; the company compares the Logic Drive with an SSD, with SSD storing data memory and Logic Drive storing computing logic.
Exhibits
The offered technologies include Logic Drive multi-chip packaging, FPMCP advanced multi-chip packaging, NVM for FPGA configuration data, Glass Panel with embedded TGV Connectors, and UTVC thermal solutions. The glass-substrate multi-chip packaging offering includes embedded TGV Connectors. For heterogeneous integration, the FPMCP framework can combine chips fabricated at different technology nodes such as 5 nm, 7 nm, 10 nm, or nodes less advanced than 10 nm, and can integrate functions such as CPU, GPU, ASIC, SOC, PMIC, FPGA, SRAM, DRAM, Flash, and MRAM in advanced multi-chip packages including Si-interposer-based, Fan-Out, and 3D stacking packages. iCometrue Company Ltd. proposed the FPMCP concept in 2016 by combining Moore's-law semiconductor chip technology with More-than-Moore advanced packaging, placing one or more FPGA chips, an NVM chip, logic-computing chips such as CPU, GPU, ASIC, or SOC, and auxiliary chips such as I/O, control, or PMIC devices into one package. Configuring or re-configuring the FPGA can define or change the FPMCP's functions and applications, allow the FPGA to cooperate with other chips in the package, and turn the package into an Application Specific Multi-Chip Package (ASMCP) for particular applications. The NVM chip stores configuration data or information for the FPGA in non-volatile memory cells, making the FPMCP non-volatile field-programmable and allowing it to become a non-volatile ASMCP for specific applications. Examples described for changing FPMCP functions include configuring the FPGA as an MCU for smart cars, robots, or industrial applications, or as a DSP for multimedia, cloud data centre, and smart-network applications. Field-Programmable Interconnection Circuits on the FPGA, using configurable switches and multiplexers, can change inter-chip connections among FPGA, logic-computing, and auxiliary chips, and can also reconfigure on-chip interconnections for different package functions. The same field-programmable logic blocks can support cooperating operations in which data from one chip is processed by the configured FPGA and returned to that chip or sent to another chip, enabling application flexibility through software-controlled hardware configuration. The FPGA can also change connections between the FPMCP and external circuits, with examples of external standards or protocols including Ethernet, PCIe, UCIe, USB, and Thunderbolt. The described I/O architecture uses large I/O circuits for external connections, small I/O circuits for FPGA-side connections, and transfer circuits such as Voltage Level Shift circuits; the text gives examples of large I/Os driving capacitive loads larger than 1 or 2 pF at voltages higher than 1 or 2 volts, while small I/Os drive loads smaller than 1 or 0.5 pF at voltages lower than 1 or 0.7 volts. Because FPGA hardware can be reconfigured after wafer processing is complete, the FPMCP concept supports changes such as communications-protocol upgrades, customized computing algorithms, hardware renewal, and security encryption without redesigning or rebuilding the other chips in the package. For Artificial Intelligence development, the FPGA-based hardware circuit can be upgraded through software programming as learning or inference algorithms are optimized, providing a reconfigurable platform during AI development. The FPGA can also cooperate with CPU and GPU chips to accelerate computation, with one described flow using CUDA to dispatch work to the GPU and Open CL to send instructions to a configured FPGA before results are returned to the CPU. The described CPU/GPU/FPGA cooperating-computation flow has the CPU analyze a job and dispatch preparation to the GPU and FPGA, the GPU return results after its assigned processing, the configured FPGA process the next operation on instructions from the CPU, and the CPU use the returned FPGA result as input for the following processing step. The NVM-to-FPGA connection is described in three forms: a standard commodity NVM chip with large I/Os coupled through an I/O chip, an FPMCP-specific NVM with small I/Os coupled directly to the FPGA and externally through the I/O chip, or an FPMCP-specific NVM that combines large and small I/Os. FPMCP structures are described for both 2D planar packages and 3D stacking packages, with interconnections among FPGA, CPU/GPU/ASIC, NVM, and I/O chips adapted to the selected NVM I/O arrangement. For glass-based packaging, glass is presented as having high Young's modulus and a coefficient of thermal expansion closely matched to silicon, and Glass Panel with embedded TGV Connectors is presented as a scalable alternative for large-size advanced multi-chip packaging. Two cited glass applications are a Glass Interposer as an alternative to Si Interposer and Molded Substrate with Embedded Silicon Bridges, and a PCB with Glass Core that uses the TGV-embedded glass panel as the PCB core to increase mechanical strength and reliability for large-size boards. The Ultra-Thin Vapor Chamber uses thin-film process technology to create a vapor chamber as thin as 100–200 μm, with a liquid/vapor closed loop and light weight for portable devices including smartphones, laptops, AR/VR headsets, and smart glasses.
Capabilities and products
- R&D of nonvolatile FPGA multi-chip packaging technology
- field-programmable multi-chip package concept development
- glass-substrate multi-chip packaging with embedded TGV connectors
- glass interposer technology
- glass-core PCB technology with embedded TGV connectors
- 100–200 μm ultra-thin vapor chamber technology