At a glance
| Booth | R7324 |
| Country | FR |
| Website | sipearl.com |
Company profile
Sipearl is a European fabless processor-design company specializing in high-performance, energy-efficient, and secure CPUs for high-performance computing (HPC), artificial intelligence, and data centers. The company was created in June 2019 to bring the European Processor Initiative (EPI) project to life and support the deployment of high-performance, energy-efficient processor technologies in Europe. Sipearl is privately held and is supported by the European Union and France; its operational activities began in January 2020. At the start of operations, the company received €7.4 million in European Union Horizon 2020 research and innovation funding and began designing its first-generation processor, Rhea1. Sipearl employs 200 people in France, Spain, and Italy. The company opened an international research and development center in Barcelona, bringing it closer to Southern European partners, including the Barcelona Supercomputing Center (BSC). Its Italian R&D center is located in Bologna, a region with high-performance-computing and AI organizations including the University of Bologna, Cineca, Italy’s largest supercomputing center, and ECMWF. Sipearl works closely with the scientific community, supercomputing centers, and leading organizations in the IT, electronics, and automotive industries; these organizations are among its stakeholders, customers, and end users. Our processor development supports European digital and technological sovereignty by addressing large-scale strategic-data processing needs in security, defense, medical research, energy, climate, and engineering. Sipearl secured a technology-licensing agreement with Arm that provides access to the scalable, secure Arm Neoverse V1 platform and its associated software and hardware ecosystem. Sipearl is the only European licensee authorized to use the Arm Neoverse V1 platform, which it uses to design the Rhea1 processor. For processor design and validation, Sipearl selected the Siemens Digital Industries Software Veloce Strato emulation platform, Ansys for semiconductor power-integrity validation and power-consumption reduction, and IP from Synopsys. Processor manufacturing is entrusted to TSMC in Taiwan; the company has completed the design and tape-out of Rhea1. Sipearl closed a €130 million Series A financing round and has launched its Series B round. The €130 million financing is the largest Series A round in the European fabless semiconductor industry. Investors and financial supporters include Arm, Bull within the Atos Group, the European Innovation Council (EIC) Fund, the French state through France 2030 and French Tech Souveraineté, and Taiwan-based Cathay Venture. The European Innovation Council also supports the company through its EIC Accelerator program. Within the HPC ecosystem, Sipearl has partnerships with Bull and HPE and collaborates with AMD, Intel, and NVIDIA to address end-user requirements. These collaborations encompass AMD Instinct accelerators, Intel’s Ponte Vecchio GPU family, and NVIDIA’s accelerated-computing and networking portfolio. Sipearl belongs to technology and research organizations including GSA, ANRT, France Digitale, France Deeptech, Teratec, and Systematic. Other memberships include JEDI Foundation, PlayFrance.digital, GIM, the Industrial Alliance on Processors and Semiconductor Technology, CISPE.cloud, and INSIDE Industry Association. Sipearl is also a member of the ETP4HPC think tank for European high-performance-computing research and innovation and of Minalogic, the digital-technology cluster in France’s Auvergne-Rhône-Alpes region. PlayFrance.digital brings together more than 300 French digital-industry participants; through its memberships, Sipearl also takes part in French and European semiconductor, deep-technology, and industrial R&D networks. The company pursues sustainable growth by promoting diversity in recruitment, using green servers hosted by Ikoula, locating offices near labor pools, and limiting paper consumption. Sipearl launched its first carbon-footprint assessment in December 2023 and published another assessment in 2025 covering 2024 figures. Our high-performance, low-power microprocessor technologies address societal and environmental needs such as earlier disease detection, more effective responses to climate change, and improvements in the quality of goods and services.
Exhibits
Our first-generation Rhea1 is a European high-performance, energy-efficient server CPU designed for HPC and artificial-intelligence workloads; it features 80 Arm Neoverse V1 cores and 61 billion transistors. Rhea1 is a highly complex server CPU designed in Europe, with computing-performance and energy-efficiency objectives for supercomputing and AI processing. Each of Rhea1’s 80 cores integrates two 256-bit Scalable Vector Extension (SVE) units, providing vector-processing capability for HPC and AI workloads. The memory architecture incorporates four stacks of in-package high-bandwidth memory (HBM), combining substantial memory capacity with high data-transfer bandwidth. Rhea1 also provides four DDR5 interfaces supporting two DIMMs per channel (2DPC) and 104 lanes of PCIe Gen5 connectivity. The capacity and bandwidth of the in-package HBM are designed to improve Rhea1 performance and energy efficiency in HPC and AI workloads, including its byte-per-flop ratio. Rhea1 uses an Arm-based architecture to deliver significant energy savings and is designed to operate with third-party GPU, AI, and quantum accelerators. The processor is designed without backdoors or kill switches and protects data through secure end-to-end network transmission. Software development can use the established Arm software ecosystem, with a wide range of compilers, libraries, and tools supporting Rhea1. Rhea1 is being manufactured by TSMC in Taiwan, following completion of the processor design. The first-generation Rhea1 CPU is scheduled for release at the end of 2026. Rhea1 will equip JUPITER in Germany, Europe’s first exascale supercomputer; exascale computing denotes one billion billion calculations per second. JUPITER is operated by Forschungszentrum Jülich and built by a consortium of Bull and ParTec; Sipearl won the contract to equip this European exascale system. The second-generation Rhea2 processor will be used in the scalar-computing partition of the Alice Recoque supercomputer in France, the second European exascale system. Alice Recoque will be installed at the CEA TGCC facility in Bruyères-le-Châtel near Paris, and Bull has been awarded the contract for the supercomputer. The Alice Recoque procurement was announced by EuroHPC JU and the Jules Verne consortium, which includes GENCI, CEA, SURF, and GRNT. Rhea1 and subsequent CPU generations are intended for supercomputers and servers tackling scientific, industrial, and societal challenges in security, defense, medical research, energy, climate, and engineering. The processors address strategic applications requiring substantial computing power, while their design goals include reducing the carbon footprint and strengthening European technological independence.
Capabilities and products
- HPC/AI data-center CPU design