Primarius Technologies Co.,Ltd.

At a glance

Company profile

Primarius Technologies Co.,Ltd. is a globally competitive EDA company focused on Design Technology Co-Optimization, or DTCO, and uses data-driven approaches to accelerate time-to-market and improve the YPPA of circuit design and manufacturing. Its design enablement technologies cover semiconductor parametric testing, advanced SPICE modeling, PDK development, and standard cell library development. The company combines SPICE and FastSPICE simulation technologies with a flexible custom-design platform to support a DTCO-enabled design flow for complex memory, analog, and mixed-signal designs. Its DTCO solution includes SPICE model, PDK, and standard cell library development technologies. Primarius Technologies Co.,Ltd. is listed as 688206.SH and describes itself as China's first publicly listed EDA company. The company is building an EDA plus IP chip foundation, using AI to advance DTCO methodology, deepen coordination between chip design and process platforms, and connect upstream, downstream, and EDA partners into a semiconductor ecosystem. In 2025, the company introduced 上国投 and 临港科创 as strategic shareholders, received Shanghai's Manufacturing Single Champion recognition, and was named among the first Lingang New Area chain-leader enterprises. In 2024, it was selected among the first Shanghai Innovative Enterprise Headquarters, was recognized as a Shanghai municipal enterprise technology center, introduced a high-precision source measurement unit with proprietary intellectual property, and led the establishment of the Shanghai EDA/IP Innovation Center. In 2023, Primarius Technologies Co.,Ltd. acquired European design-EDA solution provider Magwel and released the NanoSpice Pro X FastSPICE simulator and VeriSim digital logic circuit simulator. In 2022, it released the NanoDesigner full-custom design platform and NanoCell characterization solution, established an EDA-focused investment fund, and launched an EDA ecosystem based on the DTCO concept. In 2021, the company acquired Korean SoC design-EDA solution provider Entasys and completed its initial public offering and listing on the STAR Market. In 2020, the SDEP target-driven automatic model-extraction platform received a million-dollar-level order from a leading global IDM, while in 2019 the company acquired domestic EDA company 博达微 and released NanoSpice Pro. In 2018, BSIMProplus was adopted by several leading semiconductor foundries and the company released the FS-Pro semiconductor parametric test system. From 2016 to 2017 it released the 9812DX low-frequency-noise test system and saw broad NanoSpice adoption, while earlier milestones included NanoSpice Giga and ME-Pro in 2014 to 2015, NanoSpice and 9812D in 2012 to 2013, and company registration plus NanoYield in 2010 to 2011. Its listed global locations include Shanghai Zhangjiang, Shanghai Lingang, Guangzhou, Seoul, Gyeonggi-do, Beijing Chaoyang, Beijing Yizhuang, Jinan, Singapore, San Jose, and Hsinchu.

Exhibits

The manufacturing-EDA portfolio includes BSIMProPlus for baseband modeling, SDEP for model-extraction automation, PCellLab for PCell development, NanoCell for library characterization, LibWiz for library validation, FabLitho for lithography modeling and simulation, and FAR for automated reticle design. Custom and analog design tools include NanoDesigner SE for schematic capture, NanoDesigner LS for layout editing, NanoDesigner iV for interactive physical verification, NanoDesigner Optimizer for design optimization, NanoSpice, NanoSpice X, and NanoSpice Giga for SPICE simulation, NanoSpice Pro and Pro X for FastSPICE simulation, NanoSpice MS for mixed-signal simulation, and NanoWave for waveform analysis. Circuit and SoC analysis products include NanoSpice CCK for static and dynamic circuit checking, NanoYield for yield analysis, NanoSpice SI for signal integrity, PathInspector for critical-path analysis, PTM for power-device and power-design analysis, VeriSim for digital simulation, NavisPro for floor planning, and PadInspector for chip-to-package connectivity verification. The IP portfolio lists high-reliability eNVM products MTP, OTP, eFlash, and EEPROM, together with RF IP for BLE/BT, Wi-Fi6 2.4G & 5G, SLB/SLE, UWB, POR/PDR/BOR/Bandgap, LDO, DCDC, and PMU. High-performance and low-power analog IP includes PLL, RC OSC, Crystal OSC, ADC, and DAC, while interface and foundation offerings include JESD204B/C, PCIE, USB, SATA, SAS, MIPI, LVDS, DisplayPort/eDP, and Standard Cell IP. Testing products include FS-Pro and FS800 semiconductor parametric analyzers, 9812DX, 9812E, and 9812HF low-frequency-noise systems, the 9812AC AC dynamic-noise system, LabExpress electrical-parameter testing software, and the P1800 source measure unit. Engineering offerings include data acquisition and characterization, SPICE model extraction and QA, testkey design and layout, new-device solutions, PDK development and verification, standard-cell-library and IP-core characterization and development, IC simulation and verification, and standard-cell-library design acceleration. The DTCO platform and optimization engine are described as optimizing process recipes, device performance, circuit YPPA, and reliability, while the Design Enablement flow shortens the SPICE-modeling, PDK, and standard-cell-library development cycle from months to weeks. Primarius Technologies Co.,Ltd. provides one-stop, data-driven Design Enablement solutions for foundries and fabless companies, spanning device characterization testing through SPICE modeling, PDK, and standard cell library development, with engineering services and related technical training. The NanoSpice family combines parallel high-capacity SPICE simulation, dual-engine FastSPICE, and mixed-signal Cosim, supporting circuit checks, signal integrity, high-sigma yield, transistor aging, and custom simulation and verification for Flash, DRAM, SRAM, general analog, power management, Serdes, ADC, DAC, clock-tree, and other circuits. NanoDesigner is a flexible, extensible custom EDA design platform integrated with the NanoSpice series, supports industry-standard tools and databases such as OpenAccess, and combines schematic and layout design, simulation and analysis, physical verification, and design automation for memory and analog circuits. The standard-cell-library design solution uses distributed parallel architecture plus cell-circuit analysis and extraction algorithms, with built-in high-precision NanoSpice simulators covering automated library design, characterization, and verification. The test-system line combines semiconductor characterization instruments with EDA products to provide data-driven EDA-flow solutions, and its parametric-test systems are used to measure and monitor device parameters for manufacturing-process evaluation and chip-design optimization. FS-Pro is a configurable semiconductor electrical-characterization system for low-frequency characterization of semiconductor devices, LED materials, two-dimensional-material devices, metals, advanced materials, new devices, and device-reliability research. FS-MEMS integrates sensor-structure parameter testing, supports one-button dynamic and static testing of IV, CV, leakage, resistance, resonant frequency, Q value, quadrature coefficient, and -3dB bandwidth, and supports parallel multichannel testing for gyroscopes, accelerometers, pressure sensors, optical flow meters, infrared sensors, and other MEMS devices. FS800 uses a modular architecture and data bus to combine IV, CV, fast waveform generation and testing, low-frequency-noise testing, and high-speed time-domain acquisition in one system, with LabExpress algorithms supporting extensible tests and customized flows. The 981X low-frequency-noise family covers mature processes through 28/14/10/5/3nm research, IC design, and academic use, while 9812AC is presented as a commercial AC-noise test system for semiconductor research. The ATS wafer-level automatic measurement solution is based on FS-Pro plus in-house hardware and control software, and can integrate IV, CV, pulsed IV, high-speed time-domain acquisition, low-frequency-noise, and reliability tests. LabExpress supports preset templates, custom test algorithms and flows, wafer mapping, and large-scale data management, while the P1800 series combines precision sourcing, voltage, current and resistance measurement, transient testing, pulse and arbitrary-waveform generation and measurement, and four-quadrant IV analysis. The IP offering spans high-reliability embedded memory, high-performance and low-power analog, wireless RF, high-speed interfaces, and foundation IP for high-end SoC design and production in IoT, consumer electronics, industrial, and automotive electronics. High-reliability memory IP includes MTP, OTP, eFlash, and EEPROM, while RF and mixed-function IP includes BLE/BT, Wi-Fi6 2.4G & 5G, SLB/SLE, UWB, POR/PDR/BOR/Bandgap, LDO, DCDC, and PMU. Analog IP includes PLL, RC OSC, Crystal OSC, PVT/Glitch Sensor, ADC, DAC, and CODEC, with the portfolio described around stable data storage, precision signal processing, high-speed transmission, low power, portability, and production stability. The interface and foundation portfolio includes JESD204B/C, SerDes, UCle, PCIE, USB, SATA, SAS, MIPI, LVDS, CVI, DisplayPort/eDP, Standard Cell, SRAM, GPIO, and eFUSE, supporting logic, storage, port interaction, safety-fuse functions, display, data transmission, and chip-to-chip connectivity. The IP system is described as having undergone signal simulation and multi-process batch tape-out verification, with standardized, modular, reusable architecture for high-throughput, low-latency applications in data centers, smart terminals, automotive electronics, and other high-performance-chip production scenarios. The one-stop technical-development service combines the company's EDA-flow products and professional test systems with more than ten years of experience serving leading design and manufacturing companies to provide Design Enablement development. Its wafer-testing services cover intra-wafer, inter-wafer, temperature, electrical-performance, statistical-characteristic, baseband, RF, and reliability testing, and the company states that it has delivered more than 30,000 hours of test-service projects. The SPICE-modeling team states that it has more than 10 years of outsourced modeling experience for leading global foundries, covering process technologies from 0.35 micrometer to 7 nanometer for digital logic, analog, memory, and RF chip design and manufacturing. Testchip design and test-structure layout services support process development and debugging, device and circuit performance verification and optimization, process-reliability evaluation, and development of SPICE-model-based PDKs, standard cell libraries, and other IP. New-device solutions target high-voltage and ultra-high-voltage power devices, third-generation compound-semiconductor devices, superconducting quantum devices, and ultra-low-temperature MOS applications. PDK development services use NanoDesigner, PCellLab, PQLab, and engineering expertise to provide deeply customized PDK development and verification solutions intended to shorten development cycles and support delivery quality. IP-development services use a large-scale EDA computing center and the company's EDA-flow products to provide IP development, K-library services, chip customization, ASIC back-end design, technical consulting, and talent training for domestic and overseas customers. The custom-design EDA line centers on NanoDesigner, a flexible and extensible full-custom design environment with a high-precision SPICE engine for schematic design, layout editing, and interactive in-design physical verification across analog, mixed-signal, RF, memory, and panel circuits. Its simulation family includes NanoSpice, NanoSpice X, NanoSpice Giga, NanoSpice Pro, NanoSpice Pro X, NanoSpice MS, and NanoWave, covering high-precision SPICE, FastSPICE, mixed-signal simulation, and large-capacity waveform viewing. The circuit-analysis set includes NanoSpice CCK for dynamic and static circuit checking, NanoYield for high-sigma yield analysis, NanoSpice SI for signal integrity, PathInspector for transistor-level critical-path analysis, PTM for power-device and power-chip verification, RNi for power-network distribution analysis, and ESDi for chip-level HBM ESD analysis. NanoYield is described as a representative circuit-analysis tool intended to shorten circuit-design cycles, improve circuit quality and reliability, and reduce risk and manufacturing cost. This full-custom design and simulation flow is positioned for multiple manufacturing processes and circuit types under an application-driven DTCO methodology. NanoSpice Pro is an in-house FastSPICE simulator with a dual-engine architecture for large-capacity circuit simulation. It targets verification of large memories including DRAM, SRAM, Flash, and MRAM, as well as FPGA, custom digital, and system-on-chip designs. Its FastSPICE algorithms, intelligent topology recognition, and automatic partitioning are used to increase simulation speed and capacity for advanced-process verification. The adaptive dual engine combines a digital transistor-level engine with a giga-scale analog engine to preserve analog accuracy and digital performance in mixed-signal designs. The one-stop memory simulation flow covers memory-cell design, array and compiler verification, memory characterization, and full-chip verification, and the product is stated to deliver performance of more than 10 times that of comparable simulators. Additional capabilities include RC reduction, model calculation, multi-process support, DSPF back-annotation, SOA checking, circuit checking, full-chip timing, power and functional verification, custom high-speed digital simulation, SoC verification, and cooperation with digital simulators for mixed-signal simulation. ME-Pro is a process-and-design verification and evaluation platform that takes SPICE model libraries as input for process, device, and circuit simulation analysis, verification, evaluation, interactive design, and circuit optimization. It supports device-model simulation and validation, process-platform performance evaluation, comparison of multiple process platforms or versions, and interaction among process, device, and circuit design. The platform provides hundreds of simulation-verification parameter settings and evaluation templates and embeds the NanoSpice engine with parallel-computing algorithms for faster analysis. Its applications include model QA, model comparison, process comparison, and key-circuit performance evaluation, with a shared environment for IC design, CAD, process development, SPICE-model, and PDK professionals. One case states that a leading domestic foundry completed model-library QA at four times the speed of a traditional method and automatically generated more than 1,200 charts and comparison reports. Other cases describe process-porting comparisons for a leading chip-design company and use by a leading IDM as a collaboration platform among chip design, process, SPICE-model, and PDK teams to accelerate DTCO. NanoSpice is a large-capacity, high-performance parallel SPICE simulator for demanding analog tasks such as large post-layout simulations that require capacity, speed, and precision at the same time. Its parallel simulation technology is described as handling circuits with more than 50 million components, while maintaining high-precision operation. The product lists True SPICE accuracy, standard input and output formats, SPICE compatibility, and performance of more than two times faster at the same accuracy. It is listed as validated on advanced 7nm, 5nm, and 3nm FinFET and FD-SOI processes as well as mature processes, with functions including multi-process support, SOA checking, circuit checking, and Monte Carlo analysis. Applications include general analog simulation, high-precision ADC and Serdes simulation, LCD and OLED panel-circuit simulation, and PMIC and PMU power-management simulation; a customer statement reports that Primarius Technologies Co.,Ltd. passed the 5nm process-technology certification of 三星晶圆厂. MeQLab is an open-architecture RF modeling platform covering the flow from S-parameter testing and small-signal modeling through large-signal validation. It supports RF characterization, de-embedding, characteristic analysis, parameter extraction, and customizable settings, with templates that coordinate probe stations and instruments for on-wafer IV, CV, and RF tests. The platform supports S-parameter measurement and conversion up to 110GHz. Its built-in NanoSpice engine supports baseband-to-RF model conversion, DC validation, RF-model parameter extraction, and model-library generation, while QA functions cover RF data, fitting and extraction, extensible-model, and library validation. MeQLab can automatically generate modeling and validation reports in Word, PPT, Excel, HTML, and PDF formats and supports MOS, inductor, capacitor, HEMT, and HBT RF modeling on Windows, Linux, and UNIX. A case example describes a leading domestic fab using MeQLab for RF FinFET process-model development and delivery without switching among separate measurement, de-embedding, modeling, simulation, extraction, and QA tools. NanoSpice Giga is an in-house giga-scale transistor-level SPICE simulator whose parallel engine is described as processing circuits with more than one billion elements. It is intended for memory circuits, custom digital circuits, and full-chip simulation and verification. Its True SPICE engine is used to meet accuracy requirements for power, leakage, timing, and noise at advanced process nodes. Parallel simulation is used to accelerate circuit simulation without reducing simulation accuracy, and the product is positioned as a standard signoff simulator for memory IP and chip-design verification. The product supports more than one billion elements, multiprocess and multithread parallelism, advanced 7nm, 5nm, and 3nm FinFET and FD-SOI processes plus mature processes, DSPF back-annotation, SOA checking, and circuit checking. Applications include large post-layout analog verification, high-precision Flash, DRAM, SRAM, and MRAM memory-chip verification, PMIC and PMU power-management simulation, and high-precision SoC full-chip verification.

Capabilities and products

• Baseband SPICE modeling
• Automated SPICE model parameter extraction
• PCell development tools
• Standard-cell library characterization
• Standard-cell library validation
• Lithography process modeling and simulation
• Automated reticle design
• Circuit schematic design tools
• Circuit layout editing tools
• Interactive physical verification
• Circuit design optimization
• FastSPICE circuit simulation
• Mixed-signal circuit simulation
• Waveform analysis tools
• Static and dynamic circuit checking
• Signal integrity analysis
• Transistor-level critical-path analysis
• Power-device and power-supply chip design verification
• Digital circuit simulation
• Chip floorplanning
• Chip-to-package connectivity verification
• PDK development and verification
• Power-network distribution analysis
• ESD protection verification
• SoC timing analysis
• Semiconductor electrical parameter analyzers
• MEMS sensor structural-parameter test systems
• Semiconductor low-frequency noise test systems
• Dynamic AC noise test systems
• Broadband noise analyzers
• Fully automated wafer-level electrical measurement systems
• Electrical parameter test software
• Precision source measure units
• High-sigma circuit yield analysis
• Billion-element parallel SPICE circuit simulation
• RF device modeling and verification
• On-wafer S-parameter measurements up to 110GHz
• RF measurement data de-embedding
• SPICE model quality verification and comparison
• Semiconductor process-platform performance evaluation
• Wafer baseband, RF and reliability testing services
• Outsourced SPICE model development
• Test-chip structure design and layout implementation
• EDA for high-voltage and ultra-high-voltage power devices
• EDA for third-generation compound semiconductor devices
• Superconducting quantum EDA
• EDA for cryogenic MOS
• Custom chip design services
• ASIC back-end design services
• IC design technical consulting and training
• MTP embedded non-volatile memory IP
• OTP embedded non-volatile memory IP
• eFlash embedded non-volatile memory IP
• EEPROM embedded non-volatile memory IP
• BLE/BT RF IP
• Wi-Fi6 2.4G & 5G RF IP
• SLB/SLE RF IP
• UWB RF IP
• POR/PDR/BOR/Bandgap IP
• LDO IP
• DCDC IP
• PMU IP
• PLL analog IP
• RC OSC analog IP
• Crystal OSC analog IP
• PVT/Glitch Sensor analog IP
• ADC analog IP
• DAC analog IP
• CODEC analog IP
• JESD204B/C interface IP
• SerDes interface IP
• UCle interface IP
• PCIE interface IP
• USB interface IP
• SATA interface IP
• SAS interface IP
• MIPI interface IP
• LVDS interface IP
• CVI interface IP
• DisplayPort/eDP interface IP
• Standard-cell IP
• SRAM IP
• GPIO IP
• eFUSE IP
• Design-technology co-optimization DTCO EDA
• Standard-cell library development
• Memory-array, compiler and full-chip verification
• Memory characterization

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