At a glance
| Booth | I3000 |
| Country | GB |
| Website | www.heronic.ai |
Company profile
HERONIC TECHNOLOGIES LIMITED automates the design of bespoke AI-semiconductor hardware, drawing on many years of research into hardware acceleration of AI algorithms at Imperial College London. The team addresses compute-occupancy limitations in current AI chips at the architectural level as it works on the next generation of AI processors. HERONIC TECHNOLOGIES LIMITED offers specialized semiconductor IP for specific applications, optimized for FPGA and ASIC deployment with customizable objectives ranging from low latency to resource-minimal strategies. Its MOSAIC design-automation toolflow integrates AI models and physical constraints and searches for an optimal accelerator design for a target AI application and technology pair. The company positions this automated design approach around deterministic, low-latency, energy-efficient AI inference and around improving efficiency and time to market. The team reports numerous publications in top-tier conferences and journals and state-of-the-art FPGA results in object detection, human action recognition, and image classification, alongside award-winning results from AMD and a state-of-the-art result on the MLCommons MLPerf Tiny benchmark. As an Altera Solutions Acceleration Partner, HERONIC TECHNOLOGIES LIMITED co-published a whitepaper reporting 1.9× greater performance over Nvidia devices, 34 x lower latency, and 28x compute efficiency. HERONIC TECHNOLOGIES LIMITED views Taiwan's position at the heart of the global semiconductor supply chain as a natural ecosystem for partnerships that bring efficient, automated AI acceleration into next-generation FPGA and ASIC-based systems. The company is seeking collaborations with Fabless SoC and ASIC companies building real-time video and audio chips, OEMs using FPGA devices, ODM partners developing FPGA-based processing systems, and sales, distribution, EDA, and IP ecosystem partners.
Exhibits
The semiconductor IP portfolio is organized into domain-specific product suites built on the MOSAIC design-automation toolflow and optimized for FPGA and custom-silicon deployment with high performance at minimal power. Within Real-Time Visual Intelligence, IRIS: Video Enhancement provides AI-accelerated video-processing IP for upscaling, motion enhancement, and noise reduction with ultra-low-latency optimization on FPGA and custom silicon. The listed visual functions include Super Resolution, Denoising, Frame Rate Conversion, and HDR Tone Mapping. For bespoke design services, MOSAIC accepts a trained AI model, a target technology platform such as an FPGA or process node, and Power, Performance and Area objectives and constraints. Supported AI-model inputs include ONNX, PyTorch, and TF, while the technology target can be an FPGA or ASIC node. Before any RTL line is written, MOSAIC analyzes the workload and produces early estimates for resource and LUT utilization, power consumption and energy, latency, achievable throughput, and related PPA behavior. The automated flow then produces hardware for the specified use case and delivers production-ready customized RTL and netlists described as Pareto-optimal for PPA and ready for synthesis, place-and-route, and tape-out. This workflow gives HERONIC TECHNOLOGIES LIMITED an automated route from AI model and physical constraints to a customized accelerator architecture and implementation output. Supported applications include Super Resolution, Frame Interpolation, Denoising, HDR Tone Mapping, Object Detection, Object Tracking, Semantic Segmentation, and Anomaly Detection. The application list also includes Noise Suppression, Speech Enhancement, Keyword Detection, Channel Estimation, MIMO Beamforming, Active Speaker Detection, and Signal Classification. Further supported workloads include Data Compression, Pattern Matching, Text Classification, and LLM Inference. Across these workloads, the company presents MOSAIC and its specialized silicon IP as a way to automate bespoke AI-hardware design for deterministic, low-latency, energy-efficient inference on FPGA and custom silicon.
Capabilities and products
- automated design of bespoke AI-semiconductor hardware
- hardware co-design with AI models and physical constraints
- semiconductor IP for FPGA/ASIC deployment
- automated PPA optimization for AI accelerators
- pre-RTL resource, power and throughput estimation
- production-ready customized RTL and netlists
- ultra-low-latency AI video-enhancement IP
- hardware acceleration for Super Resolution/Denoising/Frame Rate/HDR
- AI acceleration for object detection/tracking/segmentation/anomaly detection
- AI acceleration for noise suppression, speech enhancement and keyword detection
- LLM inference hardware acceleration