At a glance
| Booth | T9404 |
| Country | FR |
| Website | aniah.fr |
Company profile
Aniah is a semiconductor EDA company specializing in exhaustive electrical verification, with OneCheck® identified as its flagship solution for analyzing electrical behavior in integrated-circuit designs. Its Smart Network Analysis is designed to reduce false errors by a factor of 100 to 1000 while accurately modeling voltages in complex circuitry, opening additional reliability-verification possibilities for complex ICs. Aniah's Pseudo-Spice Engine supports 100% of circuit topologies and is intended to detect errors that occur only under specific conditions, including errors the company says conventional Spice simulators cannot detect. The verification approach was built from the ground up with the stated objective of removing the burden of false errors, so design teams can focus attention on electrical issues that require investigation. Aniah positions its technology for IDM and design-house teams that face demanding expectations for design quality, delivery schedules, and risk assessment, and it describes customer experience throughout the development process as an operating priority. The company seeks partnerships that go beyond a transactional customer-supplier relationship, using partner feedback and functionality requests as inputs for product improvement and new capabilities. Aniah states that it plans to bring new functionality to its product every year and that its consultants work with key customer participants to consider future design flows and design-process optimization. Its technical publications address electrical-rule checking, false positives and false negatives, conditional high-impedance nets, mixed-signal verification, full-chip electrical errors, and the role of design intent when AI is applied to analog design.
Exhibits
OneCheck® applies a circuit-analysis algorithm designed from scratch, with Aniah stating performance of 100x faster and a detection capacity intended to support exhaustive electrical verification at full-chip scale. The analysis is optimized for debugging and supports seamless information sharing between IC designers, allowing verification results to move directly into collaborative debug activity instead of remaining isolated in a checking tool. At transistor level, the product targets high-accuracy full-chip verification and detection of 100% of targeted errors, combining the company's exhaustive-verification positioning with transistor-scale analysis. Aniah also describes large-scale deployment so design engineers can debug errors quickly, rather than limiting the verification method to a small specialist group or a narrow signoff stage. Coverage goals include 100% of the operating range of circuits, specifically 100% of power modes and 100% of signal states, to address errors that may appear only under particular electrical conditions. For a mixed-signal analysis with multiple power scenarios on an IC containing 20 million transistors, Aniah states a run time of 1 second. The optimized flow includes 12 types of built-in design-error rules supported out of the box, giving verification teams predefined checks within the analysis environment. Aniah reports 14 tape-outs as silicon success evidence, stating that the solution has been proven correct on silicon across those tape-outs. Smart Network Analysis further addresses false-error reduction and voltage modeling in complex circuits, while the Pseudo-Spice Engine is intended to catch condition-dependent issues across all circuit topologies. The product's verification scope is therefore aimed at complex IC design closure where teams need full-chip transistor-level checking, broad operating-state coverage, fast debug, and fewer false errors in the same workflow.
Capabilities and products
- full-chip electrical verification
- full-chip transistor-level verification
- Smart Network Analysis false-error reduction
- Pseudo-Spice verification across circuit topologies
- coverage of all power modes and signal states